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HANBit
HSD16M64D8B
Synchronous DRAM Module 128Mbyte (16Mx64-Bit), DIMM, 4Banks, 4K Ref., 3.3V Part No. HSD16M64D8B
GENERAL DESCRIPTION
The HSD16M64D8B is a 16M x 64 bit Synchronous Dynamic RAM high density memory module. The module consists of eight CMOS 2M x 16 bit with 4banks Synchronous DRAMs in TSOP-II 400mil packages on a 168-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD16M64D8B is a DIMM(Dual in line Memory Module) and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.
FEATURES
* Part Identification
HSD16M64D8B-10 HSD16M64D8B- 13 * Burst mode operation * Auto & self refresh capability (4096 Cycles/64ms) * LVTTL compatible inputs and outputs * Single 3.3V 0.3V power supply * MRS cycle with address key programs - Latency (Access from column address) - Burst length (1, 2, 4, 8 & Full page) - Data scramble (Sequential & Interleave) * JEDEC standard * All inputs are sampled at the positive going edge of the system clock * The used device is2Mx16Bitx4Banks SDRAM : 100MHz ( CL=2) : 133MHz ( CL=3) HSD16M64D8B-10L : 100MHz ( CL=3)
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PIN ASSIGNMENT
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol Vss DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 DQ8 Vss DQ9 DQ10 DQ11 DQ12 DQ13 Vcc DQ14 DQ15 NC NC Vss NC NC Vcc /WE DQM0 PIN 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Symbol DQM1 /CS0 DU Vss A0 A2 A4 A6 A8 A10 BA1 Vcc Vcc CLK0 Vss NC /CS2 DQM2 DQM3 NC Vcc NC NC NC NC Vss DQ16 DQ17 PIN 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Symbol DQ18 DQ19 Vcc DQ20 NC NC CKE1 Vss DQ21 DQ22 DQ23 Vss DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 Vss CLK2 NC WP SDA SCL Vcc PIN 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Symbol Vss DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 DQ40 Vss DQ41 DQ42 DQ43 DQ44 DQ45 Vcc DQ46 DQ47 NC NC Vss NC NC Vcc /CAS DQM4 PIN 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140
HSD16M64D8B
Symbol DQM5 NC /RAS Vss A1 A3 A5 A7 A9 BA0 A11 Vcc CLK1 NC Vss CKE0 NC DQM6 DQM7 NC Vcc NC NC NC NC Vss DQ48 DQ49
PIN 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
Symbol DQ50 DQ51 Vcc DQ52 NC NC NC Vss DQ53 DQ54 DQ55 Vss DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 Vss CLK3 NC SA0 SA1 SA2 Vcc
PIN NAMES
Pin Name A0 ~ A11 DQ0 ~ DQ63 CKE0 ~CKE1 /RAS /WE Vcc SDA DU Function Address input (Multiplexed) Data input/output Clock enable input Row address strobe Write enable Power supply (3.3V) Serial data I/O Do t use Pin Name BA0 ~ BA1 CLK0 ~ CLK3 CS0 /CAS DQM0 ~ 7 Vss SCL NC Function Select bank Clock input Chip select input Column address strobe DQM Ground Serial clock No connection
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FUNCTIONAL BLOCK DIAGRAM
DQ0-63
CKE0 /CAS /RAS /CE0
HSD16M64D8B
CKE CAS RAS CE CKE CAS RAS CE CKE CAS RAS CE CKE CAS RAS CE CKE CAS RAS CE CKE CAS RAS WE WE WE WE WE
U1
A0-A11
CLK DQ0-15 UDQM BA0-1 LDQM CLK DQ16-31 UDQM
CLKA DQM0 DQM1
U2
A0-A11
DQM2 DQM3 CLKB DQM4 DQM5
/CE2
BA0-1 LDQM CLK DQ32-47 UDQM
A0-A11
U3
BA0-1 LDQM CLK DQ48-63 UDQM
U4
A0-A11
DQM6 DQM7 CLKC DQM0 DQM1
BA0-1 LDQM CLK DQ0-15 UDQM BA0-1 LDQM CLK DQ16-31 UDQM BA0-1 LDQM CLK DQ32-47 UDQM BA0-1 LDQM CLK DQ48-63 UDQM BA0-1 LDQM
U5
A0-A11
/CE1
U6
WE A0-A11
DQM2 DQM3 CLKD DQM4 DQM5
/CE3
CE CKE CAS RAS CE CKE CAS RAS CE
U7
WE A0-A11
U8
WE A0-A11
DQM6 DQM7
/WE A0 - A11 BA0-1
Vcc Vss
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Two 0.1uF Capacitors per each SDRAM
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PIN FUNCTION DESCRIPTION
Pin CLK /CE Name System clock Chip enable CLK, CKE and DQM Input Function
HSD16M64D8B
Active on the positive going edge to sample all inputs. Disables or enables device operation by masking or enabling all inputs except
Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. CKE Clock enable Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. Row/column addresses are multiplexed on the same pins. A0 ~ A11 Address Row address : RA0 ~ RA11, Column address : CA0 ~ CA8 Selects bank to be activated during row address latch time. BA0 ~ BA1 Bank select address Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. /RAS Row address strobe Enables row access & precharge. Column address /CAS strobe /WE Write enable Latches data in starting from CAS, WE active. Data input/output DQM0 ~ 7 mask DQ0 ~ 63 Vcc/Vss supply/ground Data input/output Power Blocks data input when DQM active. (Byte masking) Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic. Makes data output Hi-Z, tSHZ after the clock and masks the output. Enables column access. Enables write operation and row precharge. Latches column addresses on the positive going edge of the CLK with CAS low.
ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on Any Pin Relative to Vss Voltage on Vcc Supply Relative to Vss Power Dissipation Storage Temperature
SYMBOL VIN ,OUT Vcc PD TSTG
RATING -1V to 4.6V -1V to 4.6V 8W -55oC to 150oC
Short Circuit Output Current IOS 50mA Notes: Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70C) ) PARAMETER Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage SYMBOL Vcc VIH VIL VOH VOL MIN 3.0 2.0 -0.3 2.4 TYP. 3.3 3.0 0 MAX 3.6 Vcc+0.3 0.8 0.4
HSD16M64D8B
UNIT V V V V V
NOTE
1 2 IOH = -2mA IOL = 2mA 3
Input leakage current I IL -10 10 uA Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VCC = 3.3V, TA = 23C, f = 1MHz, VREF =1.4V 200 mV) DESCRIPTION Clock /RAS, /CAS,/WE,/CS, CKE, L(U)DQM Address DQ (DQ0 ~ DQ15) SYMBOL CCLK CIN CADD COUT MIN 2.5 2.5 2.5 5 MAX 4.0 5.0 5.0 6.5 UNITS pF pF pF pF
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70C) PARAMETER Operating current (One bank active) Precharge standby current in power-down mode ICC1 ICC2P ICC2PS SYMBOL TEST CONDITION Burst length = 1 tRC tRC(min) IO = 0mA CKE VIL(max) tCC=10ns CKE & CLK VIL(max) tCC= CKE VIH(min) CS* VIH(min), tCC=10ns Input signals are changed one time during 20ns CKE VIH(min) ICC2NS CLK VIL(max), tCC= 56 VERSION UNIT 75 1200 10 1120 8 8 10L 1120 mA mA mA 1 NOTE
ICC2N Precharge standby current in non power-down mode
160 mA
Input signals are stable Active standby current in ICC3P ICC3PS CKE VIL(max), tCC=10ns CKE&CLK VIL(max) tCC= 40 mA 40
power-down mode
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HSD16M64D8B
CKEVIH(min), ICC3N CS*VIH(min), tCC=10ns 240 mA
Active standby current in non power-down mode (One bank active)
Input signals are changed one time during 20ns CKEVIH(min)
ICC3NS
CLK VIL(max),
tCC=
160
Input signals are stable IO = 0 mA Operating current (Burst mode) ICC4 Page burst 1440 4Banks Activated tCCD = 2CLKs Refresh current Self refresh current Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. ICC5 ICC6 tRC tRC(min) CKE 0.2V 1760 1680 12 1680 mA mA 2 1160 1160 mA 1
AC OPERATING TEST CONDITIONS
(vcc = 3.3V 0.3V, TA = 0 to 70C) PARAMETER AC Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2 UNIT V V ns V
+3.3V
Vtt=1.4V
1200 DOUT 870 50pF*
VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA
50 DOUT Z0=50 50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
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OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) VERSION PARAMETER Row active to row active delay RAS to CAS delay Row precharge time Row active time SYMBOL -13 tRRD(min) tRP(min) tRP(min) tRAS(min) tRAS(max)
tRC(min)
HSD16M64D8B
UNIT -10 20 20 20 50 100 65 70 2 1 1 1 2 ea 70 -10L 20 20 20 50 ns ns ns ns ns ns CLK CLK CLK CLK 15 20 20 45
NOTE 1 1 1 1
Row cycle time Last data in to row precharge Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data
1 2 2 2 3 4
tRDL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 CAS latency=2
1
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop.
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted) -13 PARAMETER CLK cycle time CAS 7.5 latency=3 tCC CAS 10 latency=2 CLK to valid output delay CAS 5.4 latency=3 tSAC CAS latency=2 Output data hold time CAS 2.7 latency=3 tOH CAS latency=2
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-10 MIN 10 MAX MIN 10 1000 10 12
-10L UNIT NOTE MAX
SYMBOL MIN MAX
1000
1000
ns
1
6
6 ns 1,2
6
7
3
3 ns 2
-
3
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CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CAS CLK to output latency=3 CAS in Hi-Z latency=2 tCH tCL tSS tSH tSLZ tSHZ 6 7 2.5 2.5 1.5 0.8 1 5.4 3 3 2 1 1 6 3 3 2 1 1 6
HSD16M64D8B
ns ns ns ns ns ns ns 3 3 3 3 3 2
Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, ie., [(tr + tf)/2-1]ns should be added to the parameter.
SIMPLIFIED TRUTH TABLE
COMMAND Register Mode register set Auto refresh Refresh Self refresh Bank active & row addr. Read & column address Auto disable Auto disable Auto disable Auto disable Burst Stop Precharge Bank selection All banks Entry Exit Entry Exit H H H L H L H H X H L X X L H L H L L H L X H L H L L L X V X X H X V X X H X H X H H H X V X X H X V L L X V X X H X V X X X X X X X V X X X 7 V X L H X precharge precharge H X L H L L X V H X X precharge precharge H X L H L H X V H Entry Exit CKE n-1 H H L H CKE N X H L H X /C S L L L H L /R A S L L H X L /C A S L L H X H /W E L H H X H D Q M X X X X V BA 0,1 A10/ AP OP code X X Row address L Column Address (A0 ~ A7) Column L Address (A0 ~ A7) 4,5 6 4 4,5 4 A11 A9~A0 NOTE 1,2 3 3 3 3
Write & column address
Clock suspend or active power down
Precharge down mode DQM
power
No operation command
(V=Valid, X=Don't care, H=Logic high, L=Logic low)
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HSD16M64D8B
Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
TIMING DIAGRAMS
Please refer to attached timing diagram chart (II)
PACKAGING INFORMATION
Unit : mm
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HSD16M64D8B
2.54 mm MAX 0.25 mm MAX
1.27 mm
Gold: 1.04 0.10 mm Solder: 0.914 0.10 mm 28.250.15
1.270.08 mm
(Solder & Gold Plating)
ORDERING INFORMATION
Part Number
Density
Org.
Package
Ref.
Vcc
MAX.frq 133MHz (CL=3) 100MHz (CL=2) 100MHz (CL=3)
HSD16M64D8B-13 HSD16M64D8B-10 HSD16M64D8B-10L
128MByte 128MByte 128MByte
x 64 x 64 x 64
168 Pin DIMM 168 Pin DIMM 168 Pin DIMM
4K 4K 4K
3.3V 3.3V 3.3V
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